Method of manufacturing multilayer ceramic capacitor and multilayer ceramic capacitor
US9190213B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2013 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Apr 1, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/43
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A rectangular or substantially rectangular parallelepiped chip including first and second end surfaces and first and second side surfaces is produced by cutting a mother block along a first direction in a portion where, of conductive layers that are adjacent to each other in a stacking direction, a first one is present and a second one is not present and cutting of the mother block along a second direction in a portion where, of the conductive layers that are adjacent to each other in the stacking direction, the second one is present and the first one is not present. A first internal electrode formed from the first conductive layer is exposed at the first end and side surfaces and not exposed at either of the second end and side surfaces. A second internal electrode formed from the second conductive layer is exposed at the second end and side surfaces and not exposed at either of the first end and side surfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.