Methods and apparatus for congestion-aware buffering using voltage isolation pathways for integrated circuit designs with multi-power domains
US9190358B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2014 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Sep 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.