Three-dimensional stacked structured ASIC devices and methods of fabrication thereof
US9190392B1 · kind B1 · utility
10Cited by
2References
18Claims
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Key dates
| Filing date | May 20, 2014 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | May 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.