Current-limited level shift circuit
US9191006B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2014 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Sep 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/017509
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A current-limited level shift circuit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first current-limiting unit, a second current-limiting unit, a first NMOS transistor and a second NMOS transistor, for providing a pair of input terminals and three pairs of output terminals outputting level shift signals. The first current-limiting unit is connected between the third output terminal and the fifth output terminal, and the second current-limiting unit is connected between the fourth output terminal and the sixth output terminal, for providing the current limiting of state transition. The pair of the first output terminal and the second output terminal, the pair of the third output terminal and the fourth output terminal, and the pair of the fifth output terminal and the sixth output terminal are selectively for providing multiple choices to the second stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.