Memory controller, data storage device, and memory controlling method
US9191030B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2012 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Apr 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2906
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory controller includes a first error detection code generator for generating a first error detection code for data received from a host, a controller to write the data and the first error detection code to nonvolatile memory and to read the data and the first error detection code from the nonvolatile memory, an error detector to perform an error detection based on the data and the first error detection code that are read from the nonvolatile memory, a second error detection code generator to generate a second detection error code based on the data read from the nonvolatile memory, and a mismatch code generator to generate a mismatch code signaling the presence of an error in the data, wherein either the second error detection code or the mismatch code is selected based on the error detection and sent to the host.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.