Circuit for asynchronous communications, related system and method
US9191033B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2013 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Jan 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/51
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A completion-detector circuit for detecting completion of the transfer of asynchronous data on a communication channel with signal lines organized according to a delay-insensitive encoding (e.g., dual-rail, m-of-n, Berger encoding) comprises: logic circuitry for detecting the data on the aforesaid signal lines configured for: i) producing a first signal indicating the fact that the asynchronous data on the signal lines are stable; ii) producing a second signal indicating the fact that the signal lines are de-asserted; and an asynchronous finite-state machine supplied with the first signal and the second signal for producing a signal of detection of completion of transfer of the asynchronous data, the detection signal having: a first value, when the first signal is asserted; and a second value, when the second signal is asserted; and being on hold when neither one nor the other of said first signal and said second signal is asserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.