Clock synchronization
US9191193B1 · kind B1 · utility
9Cited by
7References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2014 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Jul 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock synchronization circuit includes a multi-phase clock generator to generate a plurality of delayed clocks, each delayed clock having a unique delay with regard to a source clock. The clock synchronization circuit further includes a selection circuit that selects one of the delayed clocks according to a phase error to form a local clock driven into a local clock path and received at the clock synchronization circuit as a received local clock. The selection circuit determines the phase error by comparing the received local clock to a reference clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.