High-performance sequence estimation system and method of operation
US9191247B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2014 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Dec 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0067
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An electronic receiver comprises sequence estimation circuitry operable to implement a sequence estimation algorithm. In the sequence estimation algorithm, each of a plurality of possible current states of the signal may have associated with it a respective Nc possible prior states and a respective M state extensions, where Nc and M are integers greater than 1. Each iteration of the sequence estimation algorithm may comprise extending each of the plurality of possible current states of the signal by its respective Nc possible prior states and its respective M state extensions to generate a respective Nc×M extended states for each of the plurality of possible current states. Each iteration of the sequence estimation algorithm may comprise, for each of the plurality of possible current states of the signal, selecting M of the respective Nc×M extended states to be state extensions for a next iteration of the sequence estimation algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.