Printed wiring board, semiconductor package, and printed circuit board
US9192044B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2013 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | May 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10734
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
First and second signal wiring patterns are formed in a first conductor layer. A first electrode pad electrically connected to the first signal wiring pattern through a first via and a second electrode pad electrically connected to the second signal wiring pattern through a second via are formed in a second conductor layer as a surface layer. A third conductor layer is disposed between the first conductor layer and the second conductor layer with an insulator interposed between those conductor layers. A first pad electrically connected to the first via is formed in the third conductor layer. The first pad includes an opposed portion which overlaps the second electrode pad as viewed in a direction perpendicular to the surface of a printed board and which is opposed to the second electrode pad through intermediation of the insulator. This enables reduction of crosstalk noise caused between the signal wirings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.