Low-temperature wafer level processing for MEMS devices

US9193583B2 · kind B2 · utility

Assignee

• The Royal Institution for the Advancement of Learning/McGill University · CA

Inventors

• Mourad El-Gamal · Brossard, CA
• Dominique Lemoine · Espanola, CA
• Paul-Vahe Cicek · Montréal, CA
• Frederic Nabki · Montréal, CA

Key dates

• Filing date: Oct 26, 2012
• Grant date: Nov 24, 2015
• Expiry date: May 26, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/1461
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

It would be beneficial to integrate MEMS devices with silicon CMOS electronics, package them in controlled environments, e.g. vacuum for MEMS resonators, and provide industry standard electrical interconnections such as solder bumps. However, to do so requires through-wafer via-based electrical interconnections. However, the fragile nature of the MEMS devices, the requirement for vacuum, hermetic sealing, and the stresses placed on metallization membranes are not present in conventional CMOS packaging. Accordingly there is provided a means of reinforcing through-wafer vias for integrated MEMS-CMOS circuits by in-filling the through-wafer electrical vias with low temperature deposited ceramic materials deposited with processes compatible with post-processing of CMOS electronics. Beneficially ceramics such as silicon carbide provide enhanced mechanical strength, enhanced expansion matching, and increased thermal conductivity in comparison to silicon and solder materials. The ceramic reinforcing may be further adapted to include micro-channels for the provisioning of liquid cooling through the structures.