Method and apparatus for integrated circuit mask patterning
US9195134B2 · kind B2 · utility
1Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2013 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Aug 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/70
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.