Patent · US Active

Method and apparatus for clock-gating registers

US9195259B1 · kind B1 · utility

2Cited by

3References

20Claims

0Family size

Assignee

Marvell Israel (M.I.S.L) Ltd. · IL

Inventors

Ofer Matiash · Netanya, IL
Ruven Torok · Nes Ziona, IL

Key dates

Filing date	Sep 27, 2011
Grant date	Nov 24, 2015
Priority date	—
Expiry date	Aug 19, 2033

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a register configured to store multiple data units, a data input generation circuit configured to combine input data for at least partially overwriting the register with the stored multiple data units to generate combined input data, and a clock-gating circuit configured to provide to the register a logically controlled gated clock signal having selectively enabled transitions. The register is overwritten with the combined input data in response to the selectively enabled transitions in the gated clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.