Exposing protected memory addresses
US9195404B2 · kind B2 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Dec 17, 2013 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Jun 2, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms for exposing a protected memory address are provided. A processing device may store a data value at a protected memory address. The protected memory address may be a control register or a status register. The processing device may identify a mirror relationship between the protected memory address and an unprotected memory address and copy the data value from the protected memory address to the unprotected memory address. The unprotected memory address may be directly accessible via an external interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.