Hardware support for performance analysis
US9195524B1 · kind B1 · utility
4Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2011 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Jul 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and other embodiments associated with echo cancellation are described. According to one embodiment, an apparatus includes a plurality of first registers configured to respectively store information related to a performance of a processor and a second register in communication with each of the plurality of first registers. The apparatus also includes logic configured to detect a trigger event; and in response to having detected the trigger event, copy the information related to the performance of the processor respectively in the plurality of first registers into the second register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.