Addressing variations in bit error rates amongst data storage segments
US9195533B1 · kind B1 · utility
1Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2013 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Jan 1, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure is related to an apparatus and methods for addressing variations in bit error rates amongst data storage segments. In a particular embodiment, an apparatus includes a controller that detects variations in bit error rates amongst different segments of a plurality of segments in a storage medium. The controller also adjusts a read/write operation parameter according to the detected variations amongst the bit error rates in the plurality of segments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.