Defect analysis system for error impact reduction
US9195566B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2013 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Oct 14, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/366
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a network interface, memory, and a processor. The processor is coupled with the network interface and memory. The processor is configured to analyze a first set of data associated with a plurality of data sources. Analyzing the first set of data associated with the plurality of data sources determines a plurality of relationships among the first set of data. The processor is configured to store indications of the plurality of relationships among the first set of data. An indication of a relationship indicates a possible software defect. The processor is configured to generate rules based, at least in part, on the first set of data associated with a plurality of data sources. A rule indicates a possible software defect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.