Multi-port memory that supports multiple simultaneous write operations
US9195622B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 2013 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | May 16, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2209
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
It is determined whether more than one half of a plurality of data blocks are addressed to a same primary memory bank in a plurality of memory banks. If not more than one half of the data blocks in the plurality of data blocks are addressed to the same primary memory bank, the plurality of data blocks are written to appropriate ones of the primary memory banks in a single clock cycle. If more than one half of the data blocks are addressed to the same primary memory bank, (i) a subset of the data blocks addressed to the same primary memory bank are written to the same primary memory bank, and (ii) one or more remaining data blocks of the data blocks addressed to the same primary memory bank are written to an additional memory bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.