Lifetime mixed level non-volatile memory system
US9196385B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 28, 2014 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Oct 28, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module, The flash controller is farther adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.