Protection of a wafer-level chip scale package (WLCSP)

US9196537B2 · kind B2 · utility

Assignee

• NXP B.V. · NL

Inventors

• Leonardus Antonius Elisabeth van Gemert · Nijmegen, NL
• Hartmut Buenning · Norderstedt, DE
• Tonny Kamphuis · Lent, NL
• Sascha Moeller · Hamburg, DE
• Christian Zenz · Graz, AT

Key dates

• Filing date: Aug 14, 2013
• Grant date: Nov 24, 2015
• Expiry date: Nov 23, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/12042
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) wafer; The wafer has a topside surface and an back-side surface, and a plurality of device die having electrical contacts on the topside surface. The method comprises back-grinding, to a thickness, the back-side surface the wafer. A protective layer of a thickness is molded onto the backside of the wafer. The wafer is mounted onto a sawing foil; along saw lanes of the plurality of device die, the wafer is sawed, the sawing occurring with a blade of a first kerf and to a depth of the thickness of the back-ground wafer. Again, the wafer is sawed along the saw lanes of the plurality of device die, the sawing occurring with a blade of a second kerf, the second kerf narrower than the first kerf, and sawing to a depth of the thickness of the protective layer. The plurality of device die are separated into individual device die. Each individual device die has a protective layer on the back-side, the protective layer having a stand-off distance from a vertical edge of the individual device die.