Latch comparator circuits and methods
US9197198B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2013 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Oct 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356069
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure includes circuits and methods for latching signals. In one embodiment, two inverters are configured back to back to latch a signal. Each inverter includes a capacitor configured between control terminals of inverter transistors. In one embodiment, the circuit is part of a comparator. First and second voltages are received on control terminals of differential transistors, and a differential output signal is coupled to two back to back inverters. In one embodiment, a circuit is disabled and a voltage on a control terminal of a transistor in an inverter is set below a reference, such as a power supply, to increase the speed of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.