Suppressing dielectric absorption effects in sample-and-hold systems
US9197235B2 · kind B2 · utility
2Cited by
6References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 28, 2014 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Aug 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Sample-and-hold (S/H) circuitry operating in track and hold phases and having a first S/H circuit with a first hold capacitor at which a first voltage value is maintained in the hold phase, and a dielectric absorption (DA)-suppressing circuit connectable to the first hold capacitor for operating the S/H circuitry in an additional phase after completing the hold phase and before entering the track phase. The DA-suppressing circuit is configured to supply the first hold capacitor, during an operation in the additional phase, with a second voltage value that is negatively correlated with the first voltage value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.