Method and system for analog-to-digital converter with near-constant common mode voltage
US9197239B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2015 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Jan 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each of two input lines to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2x where x ranges from 0 to m−1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than VADCfs/128 +VADCfs/256+VADCfs/512+VADCfs/1024 when m equals 4 and where VADCfs is the full-scale voltage of the ADC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.