Digital signal sampling method
US9197399B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2014 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Jun 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0334
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for processing a received digital signal includes generating a clock signal used for sampling the received signal by comparator which compares the received signal to a reference. A phase shifter adjusts the phase of the first clock signal to maximize the vertical eye opening of the signal at the sampling time. The phase of the clock signal may be adjusted in a first direction and a measure of vertical eye opening of the signal compared to a previous measure. If the measure of vertical eye opening has increased the signal another phase adjustment may be made in the same direction whereas if the vertical eye opening of the signal has decreased a further phase adjustment in the opposite direction may be made.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.