Distributed sequence number checking for network testing
US9197574B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 1, 2013 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Aug 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J99/00
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method of line speed sequence number checking of frames includes, in a first process, using a lowest order bit of a sequence number of a frame to assign the frame to an odd or even second process, and dispatching at least the sequence number for processing by the assigned second process. The method includes, in the first process, flagging as a first sequence error type occurrences of assigning consecutively processed frames to the same second process. The method includes, in the second processes, checking the sequence number of an incoming frame, flagging as a second sequence error type non-consecutive sequence numbers in consecutively processed incoming frames, and dispatching the frame for additional downstream processing. The method is applicable to a hierarchy of processes, and to multiplexed flows. The method can use a modulo N of the sequence number to assign the frame to one of N processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.