Observing embedded signals of varying clock domains by fowarding signals within a system on a chip concurrently with a logic module clock signal
US9201448B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2012 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Oct 31, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Observability of internal system-on-chip signals is a difficult problem and it is particularly difficult to observe and debug transactions with different clock domains. However, one embodiment provides observability of internal signals from multiple internal blocks having varying clock domains such as synchronous (common clock) and asynchronous (non common clock) domains. An embodiment provides simultaneous observability of debug data from both synchronous and asynchronous clock domains. An embodiment may also allow sending debug data from both synchronous and asynchronous domains from the SoC. One embodiment outputs internal signals on output pins of the SoC, thereby allowing transactions from one clock domain to be tracked to another clock domain and allowing for the determination of the relationship between the data of differing clock domains. Other embodiments are described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.