Memory circuit incorporating radiation-hardened memory scrub engine
US9201726B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2015 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Mar 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/183
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.