Memory device with variable code rate
US9201728B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2013 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Dec 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.