Integrated circuit and method for monitoring bus status in integrated circuit
US9201753B2 · kind B2 · utility
1Cited by
33References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2013 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Oct 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3055
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention disclose an integrated circuit and a method for monitoring a bus status in the integrated circuit. Multiple status detectors and a top layer monitor are disposed in the integrated circuit. Each status detector in the multiple status detectors is used to read status data on a branch bus that is coupled to each status detector in the multiple status detectors, and then the top layer monitor collects the status data from each status detector, and outputs the status data through an interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.