Processor instruction based data prefetching
US9201798B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2013 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Jan 14, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented method for prefetching data. The method includes: receiving one or more addresses by a prefetching unit upon execution of an enqueuing command in a first piece of program logic; enqueuing each of the received addresses to a recording-list; identifying one of the positions in the recording-list as jump position; providing the identified jump position to a frame-shifter; using a sub-list of the recording-list defined by a shiftable frame as a playback-list; executing a frame-shift command which triggers the frame-shifter to shift the frame in dependence on the jump position to provide an updated playback-list; fetching data identified by the updated playback-list from a second memory; and transferring the fetched data to a first memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.