Managing read/write locks for multiple CPU cores for efficient access to storage array resources
US9201802B1 · kind B1 · utility
23Cited by
4References
23Claims
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Key dates
| Filing date | Dec 31, 2012 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Dec 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for managing resources on a storage array having multiple CPU cores releases share locks on a resource by decrementing share lock counters associated with the CPU cores that release the share locks, regardless of whether these are the same as the CPU cores that acquired the share locks. As each CPU core changes its own share lock counter, cache trashing caused by changing share lock counters associated with other CPU cores can be avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.