Memory interconnect network architecture for vector processor
US9201828B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2012 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Aug 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3001
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a memory interconnection architecture for a processor, such as a vector processor, that performs parallel operations. An example processor may include a compute array that includes processing elements; a memory that includes memory banks; and a memory interconnect network architecture that interconnects the compute array to the memory. In an example, the memory interconnect network architecture includes a switch-based interconnect network and a non-switch based interconnect network. The processor is configured to synchronously load a first data operand to each of the processing elements via the switch-based interconnect network and a second data operand to each of the processing elements via the non-switch-based interconnect network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.