System for designing network on chip interconnect arrangements
US9202002B2 · kind B2 · utility
2Cited by
1References
20Claims
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Key dates
| Filing date | Oct 9, 2014 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Oct 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.