Digital-to-analog converter circuit and display driver
US9202430B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 31, 2014 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Jul 31, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Provided first and second reference voltage set wherein the first reference voltage set includes a part or all of reference voltages of the second reference voltage set, and a decoder including first and second sub-decoder sections that select Q reference voltages from first and second reference voltage sets according to upper bits of the input digital signal and transfer the so selected reference voltages to the first to Qth nodes, and third and fourth sub-decoder sections that select first and second voltages from the Q reference voltages transferred to the first to Qth nodes according to lower bits of the input digital signal and transfer the so selected voltages to the first to Pth nodes. The first and third sub-decoder sections are made up of first conductivity type transistors, while the second and fourth sub-decoder sections are made up of second conductivity type transistors. Also provided an amplifier circuit takes a weighted average of voltages at the first to Pth nodes at a preset weighting factors and outputs the weighted average voltage at an output terminal as an analog signal corresponding to the input digital signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.