Reference current generation in resistive memory device
US9202561B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2014 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Jun 5, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive memory device incorporates a reference current generation circuit to generate a reference current for the sense amplifier that is immune to variation in the resistance of the reference resistive memory cells. In some embodiments, the reference current generation circuit uses reference resistive memory cells configured in the low resistance state only. The reference current generation circuit generates the reference current by combining a reference cell current and a bias current. The bias current is regulated by a feedback circuit in response to changes in the reference current to maintain the reference current at a substantially constant value and having a current value being an average of the cell currents for a resistive memory cell in the high resistance state and the low resistance state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.