Semiconductor package including stacked chips and a redistribution layer (RDL) structure
US9202796B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 2013 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Feb 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package offers improved product reliability by supplying a power voltage and a ground voltage to a semiconductor chip in a secured manner using a redistribution layer (RDL) structure. The semiconductor package includes a first semiconductor chip disposed on a substrate, a second semiconductor chip disposed on the first semiconductor chip, a plurality of redistribution lines disposed on the first semiconductor chip and electrically connecting the first semiconductor chip to the second semiconductor chip, and a redistribution wire disposed on the first semiconductor chip and electrically connecting one of the redistribution lines to another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.