Method of fabricating semiconductor structure
US9202841B1 · kind B1 · utility
3Cited by
0References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 18, 2014 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Sep 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L24/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor structure is disclosed, in which a pad above a connecting section and metal structures above a functional section are formed from the same metal layer. This design enables the simultaneous formation of the pad and the metal structures by forming a single metal layer and performing thereon a selective etching process, thereby leading to the advantages of process simplification, throughput improvement and cost reduction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.