Superlattice crenelated gate field effect transistor

US9202906B2 · kind B2 · utility

Assignee

• NORTHROP GRUMMAN SYSTEMS CORPORATION · US

Inventors

• Robert S. Howell · Silver Spring, US
• Eric J. Stewart · Silver Spring, US
• Bettina Nechay · Laurel, US
• Justin Andrew Parke · Ellicott City, US
• Harlan Carl Cramer · Columbia, US
• Jeffrey David Hartman · Severn, US

Key dates

• Filing date: Mar 14, 2013
• Grant date: Dec 1, 2015
• Expiry date: Mar 14, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8503

Abstract

The present invention is directed to a device comprising an epitaxial structure comprising a superlattice structure having an uppermost 2DxG channel, a lowermost 2DxG channel and at least one intermediate 2DxG channel located between the uppermost and lowermost 2DxG channels, source and drain electrodes operatively connected to each of the 2DxG channels, and a plurality of trenches located between the source and drain electrodes. Each trench has length, width and depth dimensions defining a first sidewall, a second sidewall and a bottom located therebetween, the bottom of each trench being at or below the lowermost 2DxG channel. A crenelated gate electrode is located over the uppermost 2DxG channel, the gate electrode being located within each of the trenches such that the bottom surface of the gate electrode is in juxtaposition with the first sidewall surface, the bottom surface and the second sidewall surface of each of said trenches.