Techniques for bypassing circuits during tests
US9203412B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2013 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Jan 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/173
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes first and second signal networks, a driver circuit, and a bypass circuit. The driver circuit generates a first signal based on a second signal during a normal mode. The second signal is received from the first signal network. The bypass circuit is coupled to the driver circuit to provide a third signal generated based on the first signal to the second signal network during the normal mode. The bypass circuit receives a fourth signal from the first signal network during a test mode. The bypass circuit generates a fifth signal based on the fourth signal. The fifth signal is provided to the second signal network during the test mode. The bypass circuit prevents the driver circuit from driving a signal to the second signal network during the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.