Estimation of digital-to-analog converter static mismatch errors
US9203426B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2014 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Jun 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/74
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital-to-analog converters (DACs) are used widely in electronics. The DACs are usually not ideal and typically exhibits errors, e.g., static mismatch errors. This disclosure describes a digital calibration technique for DAC static mismatch in continuous-time delta-sigma modulators (CTDSMs). The methodology utilizes the DAC unit elements (UEs) themselves to measure each other's mismatch. There are no extra circuitries except for the logic design inside DAC drivers or comparators. The methodology is an attractive calibration technique for high performance CTDSMs, especially for high speed system in multi-gigahertz range with low over-sampling rate (OSR).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.