Run-time code parallelization with approximate monitoring of instruction sequences
US9208066B1 · kind B1 · utility
11Cited by
48References
30Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 4, 2015 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | Mar 4, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes, in a processor that executes instructions of program code, identifying a region of the code containing one or more segments of the instructions that are at least partially repetitive. The instructions in the region are monitored, and an approximate specification of register access by the monitored instructions is constructed for the region. Execution of the segments in the region is parallelized using the specification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.