Reset of processing core in multi-core processing system
US9208124B2 · kind B2 · utility
0Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2011 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | May 25, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure is directed to performing a controlled reset of one or more cores while maintaining operation of at least one other core in a multi-core processor. An initialization core may include reset logic that may detect a problematic core or core that is unresponsive or otherwise not operating properly. The initialization core may generate a packet that enables communication with the problematic core. The initialization core may send a reset packet to the problematic core to instruct the problematic core to perform a reset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.