Bump including diffusion barrier bi-layer and manufacturing method thereof
US9209122B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Dec 14, 2012 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | May 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided herein is a bump including a diffusion barrier bi-layer, the bump having: a conductive layer; a first diffusion barrier layer formed on or above the conductive layer, and comprising an alloy of nickel and phosphorus; a second diffusion barrier formed on or above the first diffusion barrier layer, and comprising copper; and a solder layer formed on or above the second diffusion barrier layer. A manufacturing method for producing a bump is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.