Multiple seal-ring structure for the design, fabrication, and packaging of integrated circuits
US9209137B2 · kind B2 · utility
1Cited by
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8Claims
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Key dates
| Filing date | Jul 16, 2014 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | Jul 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.