Fail safe circuit
US9209718B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2014 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | Jun 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02P2201/09
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Apparatus for preventing output of an input signal is disclosed. The apparatus comprises a signal control unit comprising a signal buffering unit having an input and an output, the signal buffering unit arranged to receive an input signal and pass the input signal to the output when the signal buffering unit is powered, wherein a negative power supply terminal of the signal buffering unit is arranged to be supplied by a first power source having a voltage. The signal control unit also comprises a boost circuit arranged to boost the voltage of the first power source to a boosted voltage higher than the voltage of the first power source and supply either the voltage of the first power source or the boosted voltage to a positive power supply terminal of the signal buffering unit. The signal buffering unit is powered when the boosted voltage is supplied to the positive power supply terminal of the signal buffering unit and the signal buffering unit is not powered when voltage of the first power supply terminal is supplied to the positive power supply terminal of the signal buffering unit. Also disclosed is an apparatus for providing output voltages for driving a motor as well as a moto…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.