High-speed clock skew correction for serdes receivers
US9209962B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2015 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | May 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to data communication. More specifically, the present invention provides a mechanism for determining an adjustment delay that minimizes skew error due to poor alignment between edge samples and data samples. The adjustment delay is determined by sampling edge samples and data samples using different test delays at a calibration frequency that is different from the sampling frequency. The test delay associated with the least average position between the data samples and edge samples is selected as the adjustment delay. The adjustment delay is used as a parameter when sampling data at the sampling frequency. There are other embodiments as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.