Interface for controlling the phase alignment of clock signals for a recipient device
US9213359B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2012 |
| Grant date | Dec 15, 2015 |
| Priority date | — |
| Expiry date | Jan 13, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Interface circuitry transmitting transactions between an initiator and a recipient includes: a clock input receiving a clock signal; a transaction input receiving transactions; clock outputs for outputting the clock signal; transaction outputs outputting the transactions to the recipient; and synchronizing circuits clocked by the clock signal and transmitting the transactions to the transaction output in response to the clock signal. A controllable delay circuit is provided between the clock input and the synchronizing circuits. A further synchronizing circuit configured to provide a similar delay. Phase detection circuitry is arranged to detect alignment of the received clock signals. Calibration control circuitry adjusts a delay of the controllable delay circuit during calibration until the phase detection circuitry detects alignment. The calibration control circuitry controls the controllable delay circuit to generate a delay to the clock signal in dependence upon the delay that generated the alignment detected during calibration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.