Dynamic per-decoder control of log likelihood ratio and decoding parameters
US9213600B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2013 |
| Grant date | Dec 15, 2015 |
| Priority date | — |
| Expiry date | Mar 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/45
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes one or more error-correction decoders, a buffer, at least one direct memory access (DMA) engine, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one DMA engine may couple the buffer and the one or more error-correction decoders. The at least one processor may be enabled to send messages to the at least one DMA engine. The messages may be configured to deliver DMA control information and corresponding datapath control information. Data may be read from the buffer based upon the DMA control information and delivered to the one or more error-correction decoders along with the corresponding datapath control information. The one or more error-correction decoders may be enabled to decode the data read from the buffer according to the corresponding datapath control information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.