E-fuse structure of semiconductor device
US9214245B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 3, 2014 |
| Grant date | Dec 15, 2015 |
| Priority date | — |
| Expiry date | Dec 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is an e-fuse structure of a semiconductor device having improved fusing performance so as to enable a program operation at a low voltage. The e-fuse structure includes a first metal pattern formed at a first vertical level, the first metal pattern including a first part extending in a first direction and a second part extending in the first direction and positioned to be adjacent to the first part, and a third part adjacent to the second part, the second part being positioned between the first part and the third part, the first part and the second part being electrically connected to each other, and the third part being electrically disconnected from the second part; and a second metal pattern electrically connected to the first metal pattern and formed at a second vertical level different from the first vertical level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.