Patent · US Active

Phase-lock in all-digital phase-locked loops

US9214947B2 · kind B2 · utility

2Cited by

2References

21Claims

0Family size

Assignee

Intel Mobile Communications GmbH · DE

Inventor

Stefan Mendel · Graz, AT

Key dates

Filing date	Feb 19, 2013
Grant date	Dec 15, 2015
Priority date	—
Expiry date	Jul 5, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH03L2207/50
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

This disclosure relates to an all digital phase-lock loop (ADPLL). The ADPLL determines an error generated by a digitally controlled oscillator (DCO) which is operated using a tuning word, stores information related to the error, and compensates for the error based on the stored information.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.