Video bit-rate reduction system and method utilizing a reference images matrix
US9215468B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2014 |
| Grant date | Dec 15, 2015 |
| Priority date | — |
| Expiry date | Aug 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/91
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A video bit-rate reduction system utilizing a reference images matrix and a method of operating the video bit-rate reduction system are disclosed. In one embodiment, the video bit-rate reduction system includes an encoder-side bit-rate reduction system (e.g. a video signal transmitter) with a reference images matrix matchmaker and a decoder-side bit-rate reduction system (e.g. a video signal receiver) with a reference images matrix reconstructor. The video bit-rate reduction system is designed to accommodate a reference images matrix-based symbolization, matchmaking, and reconstruction of residual signals that are processed through a support layer pathway with a high bit-rate reduction and data transmission efficiency, while retaining the high-quality of the video data without any or substantial visible degradation of image and video quality. In a preferred embodiment, a sparse linear model is applied to the reference images matrix matchmaking and the reference images matrix reconstruction for compact symbolization of the residual signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.